The present invention relates to a semiconductor device, and more particularly to a surface passivation film structure for improving the breakdown voltage and the reliability of a semiconductor substrate which includes at least a three-layer transistor structure of npn or pnp.
Various methods have been used for improving the breakdown voltage of a semiconductor device. For example, a method has hitherto been known in which, as disclosed in Japanese Patent Publication No. 52-24833, an insulating film is provided on an exposed end of a pn junction formed in a semiconductor substrate, and a resistive material film is deposited on the insulating film at a place between a pair of electrodes kept in contact with p- and n-semiconductor layers. Further, a similar method is disclosed in F. A. Selim, "High-Voltage, Large-Area Planar Devices", IEEE Electron Device Letters, Vol. EDL-2, No. 9, 1981, pages 219 to 221. In this method, in order to enhance the breakdown voltage of a semiconductor substrate having a two-layer diode structure of pn, a resistive material sheet is provided in the same manner as disclosed in the above-referred Japanese patent publication, and a semi-insulating (namely, highly-resistive) polycrystalline silicon film (hereinafter referred to as SIPOS) is used as the resistive material sheet.
However, the above techniques have been applied to a diode having a single pn junction, and have not solved the problem of the emitter-collector breakdown voltage of an npn or pnp transistor structure. In more detail, when the above techniques are applied to the collector and base layers of a transistor, the collector-base breakdown voltage is improved. However, according to the inventors' experiments, the emitter-collector breakdown voltage becomes lower, as compared with a case where the SIPOS is not provided.